The present invention relates to a semiconductor memory device, and more particularly to a trench storage memory cell structure having an isolation collar region that suppresses vertical parasitic current leakage, without significantly decreasing the cross-sectional area of the trench. The present invention is also directed to a method of fabricating such a trench storage memory cell structure.
A metal oxide semiconductor field effect transistor (MOSFET) is used in forming dynamic random access memory (DRAM) cells. A DRAM circuit typically includes an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to, memory cells is achieved by activating selective wordlines and bitlines. Typically, a DRAM cell comprises a MOSFET connected to a capacitor. The capacitor includes two electrodes that are separated by a node dielectric, while the MOSFET includes a gate and diffusion regions that are referred to as either the source or drain region, depending on the operation of the transistor.
There are different types of MOSFETs known to those skilled in the art. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Trench capacitors are frequently employed with DRAM cells. A trench capacitor is a three-dimensional structure formed into a Si-containing substrate. This is normally formed by etching trenches of various dimensions into the Si-containing substrate. Trenches commonly have N+doped polysilicon as one electrode of the capacitor (i.e., the storage node) and the other electrode of the capacitor is a buried plate that is formed via out-diffusion of dopants into a portion of the substrate surrounding the lower portion of the trench.
To prevent carriers from traveling through the substrate between adjacent devices, (e.g., transistors and capacitors) device isolation regions are formed between adjacent semiconductor devices. Generally, device isolation regions take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is via a local oxidation of silicon (LOCOS) process. LOCOS field oxidation regions are formed by first depositing a layer of nitride on the surface of the substrate and then selectively etching a portion of the nitride layer to form a mask exposing the substrate where the field oxide region will be formed. The masked substrate is then placed in an oxidizing environment and a thick oxide layer is grown at the regions exposed by the mask, forming an oxide layer extending above and below the surface of the substrate. An alternative to LOCOS field oxide regions is the use of shallow trench isolation (STI) regions. In STI, a sharply defined trench is formed in a substrate by, for example, anisotropic etching. The trench is then filled with an isolation oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions formed by STI have the advantage of providing device isolation across their entire lateral extent and of providing a more planar structure.
With continued scaling of minimum feature size in the DRAM array, reduction of the lateral dimensions (the openings) of the deep trench (DT) storage capacitor results. Further, a shift is ongoing from currently practiced cell area of 8F2 (F is the minimum linewidth of the feature size that can be patterned with lithography) for planar MOSFET cells to a cell area of 7F2 or 6F2 for planar and vertical MOSFET cells. This is driving the design opening of the DT capacitor from a 1:2 to a 1:1 width to length ratio. A reduction in the size opening of the storage trench makes filling the DT with conductive material more difficult. Further, the difficulty in filling the DT is also compounded since the collar isolation oxide thickness requirement does not scale significantly from generation to generation.
A typical trench storage memory cell is shown, for example, in FIG. 1. Specifically, the trench capacitor memory cell of FIG. 1 comprises substrate 10 having N+ bitline diffusion regions 12 formed therein. The substrate also includes a plurality of trench capacitor memory cells 14. Each trench capacitor memory cell includes trench capacitor 16 formed in a lower portion of the trench and vertical MOSFET 18 formed in an upper portion of the trench. The trench capacitor includes N+ buried plate diffusion 20 formed about the exterior walls of the trench, node dielectric 22 lining the interior walls of the trench, and storage capacitor node conductor 24 formed within the trench on the exposed walls of the node dielectric. The vertical MOSFET includes gate dielectric 26 formed on vertical sidewalls of the trench, and gate conductor 28 formed on the gate dielectric. The trench capacitors and the vertical MOSFET are isolated from each other by trench top oxide layer 30 and collar isolation oxide 32, yet the structures are in electrical communication through N+ buried strap diffusion region 34. It is noted that the N+ buried strap diffusion regions and the N+ bitline diffusion regions form the source/drain regions of the vertical MOSFET.
In the prior art structure, vertical parasitic transistor 36 exists on the sidewalls of the trench between the N+ buried strap diffusion regions and the N+ buried plate diffusion regions. The gate of the parasitic transistor is the storage capacitor node conductor of the capacitor, and one source/drain region is the N+ buried strap diffusion region and the other source/drain region is the N+ buried plate diffusion region. In the prior art structure, the collar oxide is not able to raise the threshold voltage of the parasitic transistor so that it does not conduct unless collar isolation oxide 32 is sufficiently thick; therefore excess current leakage may exist in typical prior art trench capacitor memory cells.
Suppression of the vertical parasitic transistor leakage required for long data retention time, between the storage node diffusion (i.e., buried-strap outdiffusion) and the N+ buried plate of the capacitor, along the DT sidewall is thickness of the collar isolation oxide and/or the minimum doping concentration in the deep portion of the array P-well. If the difficulty in filling the DT is alleviated by thinning the collar isolation oxide, then the doping concentration in the array P-well is generally increased to compensate for the thinner collar isolation oxide. However, by increasing the P-well concentration, data retention time is degraded. Also, having a very small DT opening within the collar isolation region adds to series resistance of the trench capacitor. An increased resistance limits the amount of charge that can be stored, which thereby degrades the yield of the memory chip.
Another problem with the prior art trench capacitor memory cell structure is that the vertical length of the collar isolation oxide detracts from the area where the storage capacitor can be formed and, if the collar oxide is formed by a deposition process, oxide extends into the trench, which decreases the cross-sectional area and thus increases the resistance. That is, prior art collar isolation oxides xe2x80x98choke offxe2x80x99 the cross-sectional area of the trench so that the resistance of the trench is increased. This makes it more difficult to exchange charge between the capacitor and the rest of the circuitry in the DRAM, namely the bitline.
In view of the above, there remains a need for providing a new and improved collar isolation region, which suppresses the vertical parasitic MOSFET leakage without the need for increasing the doping concentration of the array P-well. Any new collar isolation region provided should have a thick oxide length that does not detract from the cross-sectional area where the storage capacitor is made, and the collar isolation region of the trench should have increased isolation cross-sectional area.
One object of the present invention is to provide a trench storage memory cell structure that includes a collar isolation region that is capable of substantially suppressing the vertical parasitic current leakage between the buried-strap outdiffusion region and the buried plate of the capacitor.
Another object of the present invention is to provide a trench storage memory cell structure having a collar isolation region that includes a thick isolation region whose length does not significantly detract from the area wherein the storage capacitor is formed.
A further object of the present invention is to provide a trench storage memory cell structure that has a thick collar isolation region that does not substantially decrease the cross-sectional area of the trench.
An even further object of the present invention is to provide a trench storage memory cell structure having a collar isolation region which includes at least a thick thermal oxide region and a thinner abutting isolation region that comprises a deposited oxide or a low-k dielectric material.
These and other objects and advantages are achieved in the present invention by providing a short collar isolation region having a thick first portion that is present partially outside the trench and a thin second portion that is present inside the trench. The reduced length enhances the trench capacity, while the partial placement outside the trench increases the open trench diameter for trench fill and improves the trench series resistance.
One aspect of the present invention thus relates to a trench capacitor memory cell structure that comprises:
a plurality of trenches present in a semiconductor substrate, each of said plurality of trenches including a vertical transistor isolated from an underlying trench capacitor, and
a vertical collar isolation region having a vertical length of about 0.50 xcexcm or less present on sidewalls of each trench between said vertical transistor and said trench capacitor, said collar isolation region having a first portion that is present partially outside the trench and a second portion that is present inside the trench, said first portion is thicker than said second portion thereby reducing current leakage of an adjacent vertical parasitic transistor.
In one preferred embodiment of the present invention, the second portion of the collar isolation region comprises a low permittivity (i.e., low dielectric constant (k)) dielectric which serves to increase the threshold voltage of the vertical parasitic transistor. The terms xe2x80x9clow permittivityxe2x80x9d or xe2x80x9clow-kxe2x80x9d are used herein to denote a dielectric material having a dielectric constant that is less than Si3N4. It is noted that all dielectric constants are relative to a vacuum, unless otherwise noted.
Another aspect of the present invention is directed to a method of fabricating the above-mentioned trench capacitor memory cell structure. Specifically, the inventive method includes the steps of:
providing a plurality of trenches in a surface of a semiconductor substrate, each of said plurality of trenches having an upper region and a lower region, said lower region containing a trench capacitor formed therein;
forming a vertical collar isolation region in each of said trenches, said vertical collar isolation region having a vertical length of about 0.50 xcexcm or less and a first portion that is present partially outside the trench and a second portion that is present inside the trench, said first portion is thicker than said second portion; and
forming a vertical transistor above said vertical collar isolation region.